cys tech electronics corp. s pec. no. : c262 c3 issued date : 20 12.08.08 revised date : page no. : 1/6 dt a123 y c 3 c y s t ek product s pecification pnp digital transistors (built-in resistors ) DTA123YC3 features ? built-in bias resistors enable the configuration of an inverter circu it without connecting external input resistors (see equi valent circuit). ? the bias resistors consist of thin -film resistors with complete isolat ion to allow positive biasing of the input. they also have the advantage of almost completely eliminating parasitic effects. ? only the on/off conditions need to be set for operation, making device design easy. ? complements the dtc123yc3 ? pb-free & halogen-free package. equivalent circuit outline sot-523 DTA123YC3 r1=2.2k , r2=10 k in(b) : base out(c) : collector gnd(e) : emitter absolute maximum ratings (ta=25 c) parameter symbol limits unit supply v o ltage v cc -50 v input voltage v in -12~+5 v i o -100 ma output current i o(max) -100 ma power dissipation pd 150 mw thermal resistance, junction to ambient r ja 833 c/w operating junction and storage temp erature range tj ; tstg -55~+150 c http://
cys tech electronics corp. s pec. no. : c262 c3 issued date : 20 12.08.08 revised date : page no. : 2/6 dt a123 y c 3 c y s t ek product s pecification electrical characteristics (ta=25 c) parameter symbol min. typ. max. unit test conditions v i(off) - - -0.3 v v cc =-5v, i o =-100 a input voltage v i(on) -3 - - v v o =-0.3v, i o =-20ma output voltage v o(on) - -0.1 -0.3 v i o /i i =-10ma/-0.5ma input current i i - - -3.8 ma v i =-5v output current i o(off) - - -0.5 a v cc =-50v, v i =0v dc current gain g i 33 - - - v o =-5v, i o =-10ma input resistance r 1 1.54 2.2 2.86 k - resistance ratio r 2 /r 1 3.6 4.5 5.5 - - transition frequency f t - 250 - mhz v ce =-10v, i c =-5ma, f=100mhz* * transition frequency of the device ordering information device package shipping marking DTA123YC3 sot-523 (pb-free and halogen ?free package) 3000 pcs / tape & reel 52
cys tech electronics corp. s pec. no. : c262 c3 issued date : 20 12.08.08 revised date : page no. : 3/6 dt a123 y c 3 c y s t ek product s pecification typical characteristics d c c urre nt g a i n vs o ut put c urre nt 1 10 100 1000 0. 1 1 10 100 o u t p u t c u rre n t ---io (ma ) current gain--- hfe vo=5v o ut put v ol t a ge vs o ut put c urre nt 10 100 1000 1 10 100 o u t p u t c u rre n t ---io (ma ) output voltage---vo(on)(mv) io / ii = 20 i nput v ol t a ge vs o ut put c ur r e nt ( o n c ha r a c t e r i s t i c s ) 0.1 1 10 0. 1 1 10 100 o u t p u t c u rre n t --- io (ma ) input voltage --- vi(on)(v) vo=0.3v o ut put c ur r e nt vs i nput v ol t a ge ( o f f c ha r a c t e r i s t i c s ) 0.01 0. 1 1 10 00 . 5 1 1 . 5 2 i nput v ol t a ge --- v i (o ff)(v ) output current --- io(ma) vcc=5v po wer derat i n g cu rv e 0 20 40 60 80 100 120 140 160 0 50 100 150 200 ambient temperature---ta(c) power dissip a tion---pd(mw)
cys tech electronics corp. s pec. no. : c262 c3 issued date : 20 12.08.08 revised date : page no. : 4/6 dt a123 y c 3 c y s t ek product s pecification reel dimension carrier tape dimension
cys tech electronics corp. s pec. no. : c262 c3 issued date : 20 12.08.08 revised date : page no. : 5/6 dt a123 y c 3 c y s t ek product s pecification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cys tech electronics corp. s pec. no. : c262 c3 issued date : 20 12.08.08 revised date : page no. : 6/6 dt a123 y c 3 c y s t ek product s pecification sot-523 dimension *: typical inches s t yle: pin 1.base (input) 2.emitter (grou nd) 3.collector (output) 3-l ead sot - 523 pla s tic surface mou n ted packa g e cys t ek pa ckage code: c3 marking: 52 millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.028 0.035 0.700 0.900 e 0.028 0.035 0.700 0.900 a1 0.000 0.004 0.000 0.100 e1 0.057 0.069 1.450 1.750 a2 0.028 0.031 0.700 0.800 e 0.020* 0.500* b1 0.006 0.010 0.150 0.250 e1 0.035 0.043 0.900 1.100 b2 0.010 0.014 0.250 0.350 l 0.016 ref 0.400 ref c 0.004 0.008 0.100 0.200 l1 0.010 0.018 0.260 0.460 d 0.059 0.067 1.500 1.700 0 8 0 8 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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